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document number: mc07xsc200 rev. 2.0, 9/2013 freescale semiconductor ? advance information * this document contains certain information on a new product. ? specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2013. all rights reserved. dual high side switch (7.0 m ohm ) the 07xsc200 is one in a family of devices designed for low-voltage lighting or factory automation applications. its two low r ds(on) mosfets (dual 7.0 m ? ) can control two separate 55 w / 28 w bulbs, and/or xenon modules, and/or leds, and/or dc low voltage motors. programming, control and diagnostics are accomplished using a 16-bit spi interface. its output with selectable slew rate improves electromagnetic compatibility (e mc) behavior. additionally, each output has its own parallel input or spi control for pulse-width modulation (pwm) control if desired. the 07xsc200 allows the user to program via the spi, the fault curr ent trip levels and duration of acceptable inrush. the device has fail-safe mode to provide fail-safe functionality of the outputs in case of mcu damaged. the 07xsc200 is packaged in a pb-free power-enhanced 32 pins soic package with exposed tab. this device is powered by smartmos technology. features ?dual 7.0 m ? max high side switch (at 25 c) ? operating voltage range of 6.0 to 20 v with sleep current < 5.0 a, extended mode from 4.0 to 28 v ?8.0 mhz 16-bit 3.3 v and 5.0 v spi control and status reporting with daisy chain capability ? pwm module using external clock or calibratable internal oscillator with programmable outputs delay management ? smart overcurrent shutdown compliant to huge inrush current, severe short-circuit, overtemperat ure protections with time limited auto-retry, and fail-safe mo de, in case of mcu damage ? output off or on openload detection compliant to bulbs or leds and short to battery detection. analog current feedback with selectable ratio and board temperature feedback. figure 1. 07xsc200 simplified application diagram high side switch ek suffix pb-free 98asa00368d 32-pin exposed pad soic 07xsc200 ordering information device temperature range (t a ) package MC07XSC200EK - 40 to 125 c 32 soic vdd i/o i/o so sclk csb si i/o i/o i/o a/d vpwr fsb wake si sclk csb so rstb in0 in1 csns fsi gnd hs1 hs0 gnd load load mcu v dd v dd v dd v pwr i/o clock 07xsc200
analog integrated circuit device data ? 2 freescale semiconductor 07xsc200 1 internal block diagram figure 2. 07xsc200 simplifi ed internal block diagram gnd programmable watchdog overtemperature detection logic severe short-circuit selectable overcurrent internal regulator selectable slew rate gate driver over/undervoltage protections hs0 vpwr vdd csb sclk so si rstb wake fsb in0 fsi hs1 hs0 hs1 in1 clock detection selectable output csns v reg i dwn i up i dwn r dwn openload detections detection temperature feedback v reg short to vpwr detection charge v dd failure detection calibratable oscillator pwm module vpwr voltage clamp r dwn current recopy analog mux overtemperature prewarning v dd pump por
analog integrated circuit device data ? freescale semiconductor 3 07xsc200 2 pin connections 2.1 pinout diagram figure 3. 07xsc200 pin connection 2.2 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 22 . table 1. 07xsc200 pin definitions pin number pin name pin function formal name definition 1 rstb input reset (active low) this input pin is used to initialize the device configuration and fault registers, as well as place the device in a low current sleep mode. 2 csb input chip select (active low) this input pin is connected to a chip select output of a master microcontroller (mcu). 3 sclk input serial clock this input pin is connected to the mcu pr oviding the required bit shift clock for spi communication. 4 si input serial input this is a command data input pin connected to the spi serial data output of the mcu or to the so pin of the previ ous device of a dais y chain of devices. 5v dd input digital drain voltage (power) this is an external voltage input pin used to supply power to the spi circuit. 6 so output serial output this output pin is connected to the spi serial data input pin of the mcu or to the si pin of the next device of a daisy chain of devices. 7, 25 gnd ground ground those pins are the ground for the logic and analog circuitry of the device. these pins must be shorted to board level. transparent top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 rstb csb sclk si vdd so gnd vpwr hs1 hs1 hs1 hs1 hs1 hs1 hs1 hs1 33 vpwr wake fsb in1 in0 clock csns fsi gnd hs0 hs0 hs0 hs0 hs0 hs0 hs0 hs0
analog integrated circuit device data ? 4 freescale semiconductor 07xsc200 8, 33 vpwr power positive power supply p in 8 is a positive supply for quiet and accu rate control. pin 33 is a power supply for the high current switch. these pins must be shorted at board level. connecting a heatsink to pin 33 gu arantees optimal heat-evacuation properties. 9 to 16 hs1 output high side output protected 7.0 m ? high side power output pin to the load. those pins must be shorted at board level. 26 fsi input fail-safe input the value of the resistance connected between this pin and ground determines the state of the outputs after a watchdog time-out occurs. 27 csns output output current monitoring this pin is used to output a current proportional to the designated hs0-1 output. 28 clock input reference clock this pin is used to apply a reference cloc k used to control the outputs in pwm mode through embedded pwm module. 29 in0 input direct input 0 this input pin is used to directly control the output hs0. 30 in1 input direct input 1 this input pin is used to directly control the output hs1. 31 fsb output fault status (active low) this is an open drain configured output r equiring an external pull-up resistor to vdd for fault reporting. 32 wake input wake this pin is used to input a logic [1] si gnal so as to enable the watchdog timer function. table 1. 07xsc200 pin definitions (continued) pin number pin name pin function formal name definition
analog integrated circuit device data ? freescale semiconductor 5 07xsc200 3 electrical characteristics 3.1 maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise noted. exceeding these ratings may caus e a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings v pwr supply voltage range ? load dump at 25 c (400 ms) ? maximum operating voltage ? reverse battery v pwr(ss) 41 28 -18 v v dd supply voltage range v dd -0.3 to 5.5 v input / output voltage (4) -0.3 to v dd + 0.3 v wake input clamp current i cl(wake) 2.5 ma csns input clamp current i cl(csns) 2.5 ma hs [0:1] voltage ?positive ? negative v hs[0:1] 41 -24 v output current per channel ? nominal continuous current (1) ? short-circuit transient current ? reverse continuous current (1) i hs[0:1] 26 116 -26 a high side breakdown voltage v pwr - v hs 47 v hs[0,1] output clamp energy using single pulse method (2) e cl [0:1] 100 mj esd voltage (3) ? human body model (hbm) for hs[0:1], vpwr and gnd ? human body model (hbm) for other pins ? charge device model (cdm) corner pins (1, 27, 28, 57) all other pins v esd1 v esd2 v esd3 v esd4 8000 2000 750 500 v notes 1. continuous high side output current rating so long as maximum junction temperature is not exc eeded. calculation of maximum ou tput current using board thermal resistance is required. 2. active clamp energy using single-pulse method (l = 2.0 mh, r l = 0 ? , v pwr = 14 v, t j = 150 ? c initial). 3. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ? ), the machine model (mm) (c zap = 200 pf, r zap = 0 ? ), and the charge device model (cdm), robotic (c zap = 4.0 pf). 4. input / output pins are: in[0:1], clock, rstb, fsi, csns, si, sclk, csb, so, fsb
analog integrated circuit device data ? 6 freescale semiconductor 07xsc200 thermal ratings operating temperature ? ambient ? junction (5) t a t j - 40 to 125 - 40 to 150 ? c storage temperature t stg - 55 to 150 ? c thermal resistance thermal resistance ? junction to case ? junction to ambient (6) r ? jc r ? ja 4.0 35 ? c/ w peak pin reflow temperature during solder mounting (7) t solder 260 ? c notes 5. to achieve high reliability over 10 y ears of continuous operation, the device's conti nuous operating junction temperature sho uld not exceed 125 ? ? c. 6. device mounted on a 2s2p test board per jedec jesd51-2. 20 c/w of r ja can be reached in a real application case (4 layers board). 7. pin soldering temperature limit is for 40 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. table 2. maximum ratings (continued) all voltages are with respect to ground unless otherwise noted. exceeding these ratings may caus e a malfunction or permanent damage to the device. ratings symbol value unit
analog integrated circuit device data ? freescale semiconductor 7 07xsc200 3.2 static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power inputs battery supply voltage range ? fully operational ? extended mode (8) v pwr 6.0 4.0 ? ? 20 28 v battery clamp voltage (9) v pwr(clamp) 41 47 53 v v pwr operating supply current ? outputs commanded on, hs[0 : 1] open, in[0:1] > v ih i pwr(on) ?6.520 ma v pwr supply current ? outputs commanded off, off open-load detection disabled, hs[0 : 1] shorted to the ground with v dd = 5.5 v ? wake > v ih or rstb > v ih and in[0:1] < v il i pwr(sby) ?6.57.5 ma sleep state supply current v pwr = 12 v, rstb = wake = clock = in[0:1] < v il , hs[0 :1] shorted to ground ?t a = 25 c ?t a = 85 c i pwr(sleep) ? ? 1.0 ? 5.0 30 ? a v dd supply voltage v dd(on) 3.0?5.5v v dd supply current at v dd = 5.5 v ? no spi communication ?8.0 mhz spi communication (10) i dd(on) ? ? 1.6 5.0 2.2 ? ma v dd sleep state current at v dd = 5.5 v i dd(sleep) ??5.0 ? a overvoltage shutdown threshold v pwr(ov) 28 32 36 v overvoltage shutdown hysteresis v pwr(ovhys) 0.2 0.8 1.5 v undervoltage shutdown threshold (11) v pwr(uv) 3.3 3.9 4.3 v v pwr and v dd power on reset threshold v supply(por) 0.5?0.9v pwr(uv) recovery undervoltage threshold v pwr(uv)_up 3.4 4.1 4.5 v v dd supply failure threshold (for v pwr > v pwr(uv) ) v dd(fail) 2.2 2.5 2.8 v notes 8. in extended mode, the functionality is guaranteed but not the electrical parameters. from 4.0 to 6.0 v voltage range, the device is only protected with the thermal shutdown detection. 9. measured with the outputs open. 10. typical value guaranteed per design. 11. output will automatically recover with time limited auto-retry to instructed state when v pwr voltage is restored to normal as long as the v pwr degradation level did not go below the undervoltage power-on reset threshold. this applies to all internal device logic that is supplied by v pwr and assumes that the external v dd supply is within specification.
analog integrated circuit device data ? 8 freescale semiconductor 07xsc200 outputs hs0 to hs1 hs[0,1] output drain-to-source on resistance (i hs = 5.0 a, t a = 25 ? c) ?v pwr = 4.5 v ?v pwr = 6.0 v ?v pwr = 10 v ?v pwr = 13 v r ds_01(on) ? ? ? ? ? ? ? ? 25.2 11.2 7.0 7.0 m ? hs[0,1] output drain-to-source on resistance (i hs = 5.0 a, t a = 150 ? c) ?v pwr = 4.5 v ?v pwr = 6.0 v ?v pwr = 10 v ?v pwr = 13 v r ds_01(on) ? ? ? ? ? ? ? ? 42.8 19.1 11.9 11.9 m ? hs[0,1] output source-to-drain on resistance (i hs = -5.0 a, v pwr= -18 v) (12) ?t a = 25 ? c ?t a = 150 ? c r sd_01(on) ? ? ? ? 10.5 14 m ? hs[0,1] maximum severe short-circuit impedance detection (13) r short_01 21 47 75 m ? hs[0,1] output overcurrent detection levels (6.0 v < v hs[0:1] < 20 v) ? 28w bit = 0 ? 28w bit = 1 ochi1_0 ochi2_0 oc1_0 oc2_0 oc3_0 oc4_0 oclo4_0 oclo3_0 oclo2_0 oclo1_0 ochi1_1 ochi2_1 oc1_1 oc2_1 oc3_1 oc4_1 oclo4_1 oclo3_1 oclo2_1 oclo1_1 89.9 67 48 42 35.2 28.8 21 13.3 11.3 7.4 44.9 33.5 24 20.8 17.6 14.4 6.1 6.1 6.1 2.7 114.8 83.7 61.2 53.2 44.6 36.4 26.6 18.4 14.2 9.3 57.4 41.9 30.6 26.5 22.3 18.2 7.6 7.6 7.6 4.9 139.8 100.4 74.4 64.4 54 44 32.1 23.5 17.1 11.2 69.9 50.2 37.2 32.1 27 22 9.0 9.0 9.0 7.0 a notes 12. source-drain on resistance (reverse drain-to -source on resistance) with negative polarity v pwr . 13. short-circuit impedance calcul ated from hs[0:1] to gnd pins. value guaranteed per design. table 3. static electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 9 07xsc200 outputs hs0 to hs1 (continued) hs[0,1] current sense ratio (6.0 v < vhs[0:1] < 20 v, csns < 5.0 v) (14) ? 28w bit = 0 ? csns_ratio bit = 0 ? csns_ratio bit = 1 ? 28w bit = 1 ? csns_ratio bit = 0 ? csns_ratio bit = 1 c sr0_0 c sr1_0 c sr0_1 c sr1_1 ? ? ? ? 1/10700 1/63600 1/5350 1/31800 ? ? ? ? ? hs[0,1] current sense ratio (c sr0 ) accuracy ? (6.0 v < v hs[0:1] < 20 v) with 28w bit = 0 25 and 125 ? c ?i hs[0:1] = 12.5 a ?i hs[0:1] = 5.0 a ?i hs[0:1] = 3.0 a ?i hs[0:1] = 1.5 a -40 ? c ?i hs[0:1] = 12.5 a ?i hs[0:1] = 5.0 a ?i hs[0:1] = 3.0 a ?i hs[0:1] = 1.5 a c sr0_0_acc -15 -22 -27 -30 -20 -27 -30 -40 ? ? ? ? ? ? ? ? 15 22 27 30 20 27 30 40 % hs[0,1] current recopy accuracy with one calibration point ? (6.0 v < v hs[0:1] < 20 v) with 28w bit = 0 (15) ?i hs[0:1] = 5.0 a c sr0_0_acc (cal) -5.0 ? 5.0 % hs[0,1] current sense ratio (c sr0 ) accuracy ? (6.0 v < v hs[0:1] < 20 v) with 28w bit = 1 25 and 125 ? c ?i hs[0:1] = 3.0 a ?i hs[0:1] = 1.5 a -40 ? c ?i hs[0:1] = 3.0 a ?i hs[0:1] = 1.5 a c sr0_1_acc -25 -30 -30 -40 ? ? ? ? 25 30 30 40 % hs[0,1] current recopy accuracy with one calibration point ? (6.0 v < v hs[0:1] < 20 v) with 28w bit = 1 (15) ?i hs[0:1] = 3.0 a c sr0_1_acc (cal) -5.0 ? 5.0 % hs[0,1] c sr0 current recopy temperature drift ? (6.0 v < v hs[0:1] < 20 v) with 28w bit = 0 (16) ?i hs[0:1] = 5.0 a ? (c sr0_0 )/ ? (t) ? ? 0.04 %/ ? c notes 14. current sense ratio = i csns / i hs[0:1] 15. based on statistical analysis. it is not production tested. 16. based on statistical data: delta(c sr0 )/delta(t)={(measured i csns at t 1 - measured i csns at t 2 ) / measured i csns at room} / {t 1 -t 2 }. no production tested. table 3. static electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 10 freescale semiconductor 07xsc200 outputs hs0 to hs1 (continued) hs[0,1] current sense ratio (c sr1 ) accuracy ? (6.0 v < v hs[0:1] < 20 v) with 28w bit = 0 25 and 125 ? c ?i hs[0:1] = 12.5 a ?i hs[0:1] = 75 a -40 ? c ?i hs[0:1] = 12.5 a ?i hs[0:1] = 75 a c sr1_0_acc -20 -17 -28 -25 ? ? ? ? 20 17 28 25 % hs[0,1] current recopy accuracy with one calibration point ? (6.0 v < v hs[0:1] < 20 v) with 28w bit = 0 (17) ?i hs[0:1] = 12.5 a c sr1_0_acc (cal) -5.0 ? 5.0 % hs[0,1] current sense ratio (c sr1 ) accuracy ? (6.0v < v hs[0:1] < 20v) with 28w bit = 1 25 and 125 ? c ?i hs[0:1] = 12.5 a ?i hs[0:1] = 37.5 a -40 ? c ?i hs[0:1] = 12.5 a ?i hs[0:1] = 75 a c sr1_1_acc -20 -17 -28 -25 ? ? ? ? 20 17 28 25 % hs[0,1] current recopy accuracy with one calibration point ? (6.0 v < v hs[0:1] < 20 v) with 28w bit = 1 (17) ?i hs[0:1] = 12.5 a c sr1_1_acc (cal) -5.0 ? 5.0 % current sense clamp voltage ? csns open; i hs[0:1] = 5.0 a with c sr0 ratio v cl(csns) v dd +0.25 ? v dd +1.0 v off openload detection source current (18) i old(off) 30 ? 100 ? a off openload fault detection voltage threshold v old(thres) 2.0 3.0 4.0 v on openload fault detection current threshold i old(on) 80 330 660 ma on openload fault detection current threshold with led ?v hs[0:1] = v pwr - 0.75 v i old(on_led) 2.5 5.0 10 ma output short to v pwr detection voltage threshold ? output programmed off v osd(thres) v pwr -1.2 v pwr -0.8 v pwr -0.4 v output negative clamp voltage ?0.5 a < i hs[0:1] < 5.0 a, output programmed off v cl - 22 ? -16 v output overtemperature shutdown for 4.5 v < v pwr < 28 v t sd 155 175 195 ? c notes 17. based on statistical analysis. it is not production tested. 18. output off openload detection current is the current required to flow through the load for the purpose of detecting the exis tence of an open-load condition when the specific output is commanded off. pull-up current is measured for v hs = v old(thres) table 3. static electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 11 07xsc200 control interface input logic high voltage (19) v ih 2.0 ? v dd +0.3 v input logic low voltage (19) v il -0.3 ? 0.8 v input logic pull-down current (sclk, si) (22) i dwn 5.0 ? 20 ? a input logic pull-up current (csb) (23) i up 5.0 ? 20 ? a so, fsb tri-state capacitance (20) c so ? ? 20 pf input logic pull-down resistor (rstb, wake, clock and in[0:1]) r dwn 125 250 500 k ? input capacitance (20) cin ? 4.0 12 pf wake input clamp voltage (21) ?i cl(wake) < 2.5 ma v cl(wake) 18 25 32 v wake input forward voltage ?i cl(wake) = -2.5 ma v f(wake) - 2.0 ? - 0.3 v so high-state output voltage ?i oh = 1.0 ma v soh v dd -0.4 ? ? v so and fsb low-state output voltage ?i ol = -1.0 ma v sol ? ? 0.4 v so, csns and fsb tri-state leakage current ? csb = v ih and 0 v < v so < v dd , or fsb = 5.5 v, or csns = 0.0 v i so(leak) - 2.0 0.0 2.0 ? a fsi external pull-down resistance (24) ? watchdog disabled ? watchdog enabled rfs ? 10 0.0 infinite 1.0 ? k ? notes 19. upper and lower logic threshold voltage range applies to si, csb, sclk, fsb, in[0:1], clock and wake input signals. the wake and rstb signals may be supplied by a derived voltage referenced to v pwr . 20. input capacitance of si, csb, sclk, rstb, in[0:1], clock and w ake. this parameter is guaranteed by process monitoring but is not production tested. 21. the current must be limited by a series resistance when using voltages > 7.0 v. 22. pull-down current is with v si > 1.0 v and v sclk > 1.0 v. 23. pull-up current is with v csb < 2.0 v. csb has an active internal pull-up to v dd . 24. in fail-safe hs[0:1] depends respectively on in [0:1]. fsi has an active internal pull-up to v reg ~ 3.0 v. table 3. static electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 12 freescale semiconductor 07xsc200 3.3 dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power output timing hs0 to hs1 output rising medium slew rate (medium speed slew rate / sr[1:0] = 00) (25) ?v pwr = 14 v sr r_00 0.15 0.3 0.6 v/ ? s output rising slow slew rate (low speed slew rate / sr[1:0] = 01) (25) ?v pwr = 14 v sr r_01 0.07 0.15 0.3 v/ ? s output falling fast slew rate (high speed slew rate / sr[1:0] = 10) (25) ?v pwr = 14 v sr r_10 0.3 0.6 1.2 v/ ? s output falling medium slew rate (medium speed slew rate / sr[1:0] = 00) (25) ?v pwr = 14 v sr f_00 0.15 0.3 0.6 v/ ? s output falling slow slew rate (low speed slew rate / sr[1:0] = 01) (25) ?v pwr = 14 v sr f_01 0.07 0.15 0.3 v/ ? s output rising fast slew rate (high speed slew rate / sr[1:0] = 10) (25) ?v pwr = 14 v sr f_10 0.3 0.6 1.2 v/ ? s hs[0:1] outputs turn-on and off delay times (26)(27) v pwr = 14 v for medium speed slew rate (sr[1:0] = 00) ?t dly(on) ?t dly(off) t dly _12 80 40 130 90 180 140 ? s driver output matching slew rate (sr r /sr f ) ? v pwr = 14 v @ 25 c and for medium speed slew rate (sr[1:0] = 00) ?? sr 0.8 1.0 1.2 hs[0:1] driver output matching time (t dly(on) - t dly(off) ) ?v pwr = 14 v, f pwm = 240 hz, pwm duty cycle = 50%, @ 25 c for medium speed slew rate (sr[1:0] = 00) ?? t rf_01 0 50 100 ? s notes 25. rise and fall slew rates measured across a 5.0 ?? resistive load at high side output = 30% to 70% (see figure 4 , page 19 ). 26. turn-on delay time measured fr om rising edge of any signal (in[0 : 1] and csb) that would turn the output on to v hs[0 : 1] = v pwr / 2 with r l = 5.0 ? resistive load. 27. turn-off delay time measured from falling edge of any signal (in[0 : 1] and csb) that would turn the output off to v hs[0 : 1] = v pwr / 2 with r l = 5.0 ? resistive load.
analog integrated circuit device data ? freescale semiconductor 13 07xsc200 power output timing hs0 to hs1 (continued) fault detection blanking time (28) t fault 1.0 5.0 20 ? s output shutdown delay time (29) t detect ? 7.0 30 ? s csns valid time (30) t cnsval ? 70 100 ? s watchdog time-out (31) t wdto 217 310 400 ms on openload fault cyclic de tection time with led t old(led) 105 150 195 ms notes 28. time necessary to report the fault to fsb pin. 29. time necessary to switch-off the output in case of ot or oc or sc or uv fault detection (from negative edge of fsb pin to hs voltage = 50% of v pwr 30. time necessary for csns to be within 5% of the targeted value (from hs voltage = 50% of v pwr to 5% of the targeted csns value). 31. for fsi open, the watchdog time-out delay measured from the rising edge of rstb, to hs[0,1] output state depend on the corre sponding input command. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 14 freescale semiconductor 07xsc200 power output timing hs0 to hs1 (continued) hs[0,1] output overcurrent time step for 28w bit = 0 oc[1:0] = 00 (slow by default) oc[1:0]=01 (fast) oc[1:0]=10 (medium) oc[1:0]=11 (very slow) t oc1_00 t oc2_00 t oc3_00 t oc4_00 t oc5_00 t oc6_00 t oc7_00 t oc1_01 t oc2_01 t oc3_01 t oc4_01 t oc5_01 t oc6_01 t oc7_01 t oc1_10 t oc2_10 t oc3_10 t oc4_10 t oc5_10 t oc6_10 t oc7_10 t oc1_11 t oc2_11 t oc3_11 t oc4_11 t oc5_11 t oc6_11 t oc7_11 4.40 1.62 2.10 2.88 4.58 10.16 73.2 1.10 0.40 0.52 0.72 1.14 2.54 18.2 2.20 0.81 1.05 1.44 2.29 5.08 36.6 8.8 3.2 4.2 5.7 9.1 20.3 146.4 6.30 2.32 3.00 4.12 6.56 14.52 104.6 1.57 0.58 0.75 1.03 1.64 3.63 26.1 3.15 1.16 1.50 2.06 3.28 7.26 52.3 12.6 4.6 6.0 8.2 13.1 29.0 209.2 8.02 3.00 3.90 5.36 8.54 18.88 134.0 2.00 0.75 0.98 1.34 2.13 4.72 34.0 4.01 1.50 1.95 2.68 4.27 9.44 68.0 16.4 21.4 7.8 10.7 17.0 37.7 272.0 ms table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 15 07xsc200 power output timing hs0 to hs1 (continued) hs[0,1] output overcurrent time step for 28w bit = 1 oc[1:0] = 00 (slow by default) oc[1:0] = 01 (fast) oc[1:0] = 10 (medium) oc[1:0] = 11 (very slow) t oc1_00 t oc2_00 t oc3_00 t oc4_00 t oc5_00 t oc6_00 t oc7_00 t oc1_01 t oc2_01 t oc3_01 t oc4_01 t oc5_01 t oc6_01 t oc7_01 t oc1_10 t oc2_10 t oc3_10 t oc4_10 t oc5_10 t oc6_10 t oc7_10 t oc1_11 t oc2_11 t oc3_11 t oc4_11 t oc5_11 t oc6_11 t oc7_11 3.4 1.1 1.4 2.0 3.4 8.5 62.4 0.86 0.28 0.36 0.51 0.78 2.14 20.2 1.7 0.5 0.7 1.0 1.7 4.2 31.2 6.8 2.2 2.9 4.0 6.8 17.0 124.8 4.9 1.6 2.1 2.9 4.9 12.2 89.2 1.24 0.40 0.52 0.74 1.12 3.06 22.2 2.5 0.8 1.0 1.5 2.5 6.1 44.6 9.8 3.2 4.2 5.8 9.8 24.4 178.4 6.4 2.1 2.8 3.8 6.4 15.9 116.0 1.61 0.52 0.68 0.96 1.46 3.98 28.9 3.3 1.0 1.3 2.0 3.3 6.0 58.0 12.8 16.7 5.5 7.6 12.8 31.8 232.0 ms table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 16 freescale semiconductor 07xsc200 power output timing hs0 to hs1 (continued) hs[0,1] bulb cooling time step for 28w bit = 0 cb[1:0] = 00 or 11 (medium) cb[1:0] = 01 (fast) cb[1:0] = 10 (slow) hs[0,1] for 28w bit = 1 cb[1:0] = 00 or 11 (medium) cb[1:0] = 01 (fast) cb[1:0] = 10 (slow) t bc1_00 t bc2_00 t bc3_00 t bc4_00 t bc5_00 t bc6_00 t bc1_01 t bc2_01 t bc3_01 t bc4_01 t bc5_01 t bc6_01 t bc1_10 t bc2_10 t bc3_10 t bc4_10 t bc5_10 t bc6_10 t bc1_00 t bc2_00 t bc3_00 t bc4_00 t bc5_00 t bc6_00 t bc1_01 t bc2_01 t bc3_01 t bc4_01 t bc5_01 t bc6_01 t bc1_10 t bc2_10 t bc3_10 t bc4_10 t bc5_10 t bc6_10 242 126 140 158 181 211 121 63 70 79 90 105 484 252 280 316 362 422 291 156 178 208 251 314 146 78 88 101 126 226 583 312 357 417 501 628 347 181 200 226 259 302 173 90 100 113 129 151 694 362 400 452 518 604 417 224 255 298 359 449 209 112 127 145 180 324 834 448 510 596 717 898 452 236 260 294 337 393 226 118 130 147 169 197 1904 472 520 588 674 786 542 292 332 388 467 584 272 146 166 189 234 422 1085 582 665 775 933 1170 ms table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 17 07xsc200 pwm module timing input pwm clock range on clock f clock 7.68 ? 30.72 khz input pwm clock low frequency detection range on clock (33) f clock(low) 1.0 2.0 4.0 khz input pwm clock high frequency detection range on clock (33) f clock(high) 100 ? 400 khz output pwm frequency range using external clock on clock (32) f pwm 31.25 ? 781 hz output pwm frequency accuracy using calibrated oscillator (32) a fpwm(cal) -10 ? +10 % default output pwm frequency using internal oscillator f pwm(0) 84 120 156 hz csb calibration low minimum time detection range t csb(min) 14 20 26 ? s csb calibration low maximum tine detection range t csb(max) 140 200 260 ? s output pwm duty cycle range for f pwm = 1.0 khz for high speed slew rate (33) r pwm _1k 10 ? 94 % output pwm duty cycle range for f pwm = 400 hz (33) r pwm _400 6.0 ? 98 % output pwm duty cycle range for f pwm = 200 hz (33) r pwm _200 5.0 ? 98 % input timing direct input toggle time-out t in 175 250 325 ms auto-retry timing auto-retry period t auto 105 150 195 ms temperature on the gnd flag thermal prewarning detection (34) t otwar 110 125 140 c analog temperature feedback at t a = 25 c with r csns = 2.5 k ? t feed 1.15 1.20 1.25 v analog temperature feedback derating with r csns = 2.5 k ? (35) dt feed -3.5 -3.7 -3.9 mv/c notes 32. clock fail detector available fo r pwm_en bit is set to logic [1] and clock_sel is set to logic [0]. 33. the pwm ratio is measured at v hs = 50% of v pwr and for the default sr value. it is possible to put the device fully-on (pwm duty cycle 100%) and fully-off (duty cycle 0%). for values outside this range, a calibration is needed between the pwm duty cycle programm ing and the pwm on the output with r l = 5.0 ? resistive load. 34. typical value guaranteed per design. 35. value guaranteed per statistical analysis. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 18 freescale semiconductor 07xsc200 spi interface characteristics (36) maximum frequency of spi operation f spi ? ? 8.0 mhz required low state duration for rstb (37) t wrstb 10 ? ? ? s rising edge of csb to falling edge of csb (required setup time) (38) t csb ? ? 1.0 ? s rising edge of rstb to falling edge of csb (required setup time) (38) t enbl ? ? 5.0 ? s falling edge of csb to rising edge of sclk (required setup time) (38) t lead ? ? 500 ns required high state duration of sclk (required setup time) (38) t wsclkh ? ? 50 ns required low state duration of sclk (required setup time) (38) t wsclkl ? ? 50 ns falling edge of sclk to rising edge of csb (required setup time) (38) t lag ? ? 60 ns si to falling edge of sclk (required setup time) (39) t si (su) ? ? 37 ns falling edge of sclk to si (required setup time) (39) t si (hold) ? ? 49 ns so rise time ?c l = 80 pf t rso ? ? 13 ns so fall time ?c l = 80 pf t fso ? ? 13 ns si, csb, sclk, incoming signal rise time (39) t rsi ? ? 13 ns si, csb, sclk, incoming signal fall time (39) t fsi ? ? 13 ns time from falling edge of csb to so low-impedance (40) t so(en) ? ? 60 ns time from rising edge of csb to so high-impedance (41) t so(dis) ? ? 60 ns notes 36. parameters guaranteed by design. 37. rstb low duration measured with outputs enabled and going to off or disabled condition. 38. maximum setup time required for the 07xsc200 is the minimum guaranteed time needed from the microcontroller. 39. rise and fall time of incoming si, csb, and sclk signals sugges ted for design consideration to prevent the occurrence of dou ble pulsing. 40. time required for output status data to be available for use at so. 1.0 k ?? on pull-up on csb. 41. time required for output status data to be terminated at so. 1.0 k ?? on pull-up on csb. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v ?? v pwr ? 20 v, 3.0 v ? v dd ? 5.5 v, - 40 ? c ? t a ? 125 ? c, gnd = 0 v unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 19 07xsc200 3.4 timing diagrams figure 4. output slew rate and time delays figure 5. overcurrent shutdown protection v pwr v hs[0:1] t dly(on) t dly(off) low logic level 70% v pwr 30% v pwr sr f sr r 50%v pwr r pwm csb high logic level v hs[0:1] time time time low logic level in[0:1] high logic level time or i och1 t oc5 t oc4 t oc2 t oc1 time load current i och2 i oc1 i oc3 i oc4 i oclo4 i oclo3 i oc2 t oc3 t oc6 t oc7 i oclo2 i oclo1
analog integrated circuit device data ? 20 freescale semiconductor 07xsc200 figure 6. bulb cooling management figure 7. input timing switching characteristics i och1 t b c5 t b c4 t b c2 t b c1 previous off duration (t off ) i och2 i oc1 i oc3 i oc4 i oclo4 i oclo3 i oc2 t b c3 t b c6 i oclo2 i oclo1 si rstb csb sclk don?t care don?t care don?t care va li d valid vih vil vih vih vih vil vil vil twrstb tlead twsclkh trsi tlag tsisu twsclkl tsi(hold) tfsi 0.7 vdd 0.2 vdd 0.7vdd 0.2vdd 0.2vdd 0.7vdd 0.7vdd tcsb tenbl rstb sclk si csb 10% v dd t wrst b t enbl 10% v dd t lead t wsclkh t rsi 90% v dd 10% v dd 90% v dd 10% v dd t si(su) t wsclkl t si(hold) t fsi 90% v dd t csb t lag vih vih vil vil vih vil vih vih
analog integrated circuit device data ? freescale semiconductor 21 07xsc200 figure 8. sclk waveform and valid so data delay time so so sclk voh vol voh vol voh vol tfsi tdlylh tdlyhl t valid trso tfso 3.5v 50% trsi high-to-low 1.0v 0.7 vdd 0.2vdd 0.2 vdd 0.7 vdd low-to-high t rsi t fsi 90% v dd sclk so so voh vol voh vol voh vol 10% v dd 10% v dd 90% v dd t rso t fso 10% v dd t so(en) t so(dis) low to high high to low t valid 90% v dd
analog integrated circuit device data ? 22 freescale semiconductor 07xsc200 4 functional description 4.1 introduction the 07xsc200 is one in a family of devices designed for low-voltage lighting applications. its two low r ds(on) mosfets (dual 7.0 m ? ) can control two separate 55 w / 28 w bulbs and/or xenon modules. programming, control and diagnostics are accomplished using a 16- bit spi interface. its output with selectable slew rate improves electromagnetic compat ibility (emc) behavior. additionally, each output has its own parallel input or spi control for pulse-width modulation (pwm) control if desired. the 07xsc200 al lows the user to program via the spi, the fault current trip levels and duration of acceptable lamp inrush. the device has fa il-safe mode to provide fail-safe functionality of the outputs in case of mcu damaged. 4.2 functional pin description 4.2.1 output current monitoring (csns) the current sense pin provides a curre nt proportional to the designated hs0 : hs1 output or a voltage proportional to the temperature on the gnd flag. t hat current is fed into a ground-referenced resistor (2.5 k ? typical) and its voltage is monitored by an mcu's a/d. the output type is selected via t he spi. this pin can be tri-stated through the spi. 4.2.2 direct inputs (in0, in1) each in input wakes the device. the in0 : in1 high side input pins are also used to directly control hs0 : hs1 high side output pins. if the outputs are cont rolled by pwm module, the external pwm clock is applied to in0 pin. these pins are to be driven wi th cmos levels, and they have a passive internal pull-down, r dwn . 4.2.3 fault status (fsb) this pin is an open drain configured output requiring an external pull-up resistor to v dd for fault reporting. if a device fault condition is detected, this pi n is active low. specific device diagnosti cs and faults are reported via the spi so pin. 4.2.4 wake (wake) the wake input wakes the device. an internal clamp protects this pin from high damaging voltages with a series resistor (10 k ? typ). this input has a passive internal pull-down, r dwn . 4.2.5 pwm clock (clock) the clock input wakes the device. the pwm frequency and timing are generated from clock input by the pwm module. the clock input frequency is the selectable factor 2 7 = 128. this input has a passive internal pull-down, r dwn . 4.2.6 reset (rstb) the reset input wakes the device. this is used to initialize t he device configuration and fault r egisters, as well as place the device in a low-current sleep mode. the pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. this pin has a passive internal pull-down, r dwn .
analog integrated circuit device data ? freescale semiconductor 23 07xsc200 4.2.7 chip select (csb) the csb pin enables communication with the master micr ocontroller (mcu). when this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the mcu. the 07xsc200 la tches in data from the input shift registers to the addressed registers on the rising edge of csb . the device transfers status information from the power output to the shift register on the falling edge of csb . the so output driver is enabled when csb is logic [0]. csb should transition from a logic [1] to a logic [0] state only when sclk is a logic [0]. csb has an active internal pull-up from v dd , i up . 4.2.8 serial clock (sclk) the sclk pin clocks the internal shift registers of the 07xsc200 de vice. the serial input (si) pi n accepts data into the input shift register on the falling edge of the sclk si gnal while the serial output (so) pin shifts data information out of the so line dri ver on the rising edge of the sclk signal. it is important the sclk pin be in a logic low state whenever csb makes any transition. for this reason, it is recommended the sclk pin be in a logic [0] whenever the device is not accessed ( csb logic [1] state). sclk has an active internal pull-down. when csb is logic [1], signals at the sclk and si pins are ignored and so is tri-stated (high- impedance) (see figure 10 , page 26 ). sclk input has an active internal pull-down, i dwn . 4.2.9 serial input (si) this is a serial interface (si) command data input pin. each si bit is read on the falling edge of sclk. a 16-bit stream of ser ial data is required on the si pin, st arting with d15 (msb) to d0 (lsb). the internal registers of the 07xsc200 are configured and controlled using a 5-bit addressing scheme described in table 9 , page 36 . register addressing and configuration are described in tables 10 , page 36 . si input has an active internal pull-down, i dwn . 4.2.10 digital drain voltage (vdd) this pin is an external voltage input pin used to supply power to the spi circuit. in the event v dd is lost (v dd failure), the device goes to fail-safe mode. 4.2.11 ground (gnd) these pins are the ground for the device. 4.2.12 positive power supply (vpwr) this pin connects to the positive power supply and is the source of operational power for the device. the vpwr contact is the backside surfac e mount tab of the package. 4.2.13 serial output (so) the so data pin is a tri-stateable output from the shift register. the so pin re mains in a high impedance state until the csb pin is put into a logic [0] state. the so data is capable of reporting the status of the output, the device conf iguration, the state of the key inputs, etc. the so pin changes state on the rising edge of sclk and reads out on the falling edge of sclk. so reporting descriptions are provided in table 22 , page 42 . 4.2.14 high side outputs (hs0, hs1) protected 7.0 m ? high side power outputs to the load.
analog integrated circuit device data ? 24 freescale semiconductor 07xsc200 4.2.15 fail-safe input (fsi) this pin incorporates an active internal pul l-up current source from internal supply (v reg ). this enables the watchdog time-out feature. when the fsi pin is opened, the watchdog circuit is enabled. af ter a watchdog time-out occurs, the output states depends on in[0:1]. when the fsi pin is connected to gnd, the watchdog circuit is disabled. the output states depends on in[0:1] in case of v dd failure condition, in case v dd failure detection is activated (vdd_fail_en bit sets to logic [1]). 4.3 functional internal block description figure 9. functional block diagram 4.3.1 power supply the 07xsc200 is designed to operate from 4.0 to 28 v on the vpwr pin. characteristics are provided from 6.0 to 20 v for the device. the vpwr pin supplies power to internal regulator, analog, and logic circuit blocks. the v dd supply is used for serial peripheral interface (spi) communication to configure and diagnose the device. this ic architecture provides a low quiescent current sleep mode. applying v pwr and v dd to the device will place the device in the normal mode. the device will transit to fail-safe mode in case of failures on the spi or/and on v dd voltage. 4.3.2 high side switches: hs0?hs1 these pins are the high side outputs controlling la mps located for the front of vehicle, such as 65 w/55 w bulbs and xenon-hid modules. n-channel mosfets with 7.0 m ? r ds(on) are self-protected and present exte nded diagnostics to detect bulb outage and a short-circuit fault condition. the hs output is actively clamped during turn off of inductive loads and inductive battery line. when driving dc motor or solenoid loads demand multiple switching, an external recirculation device must be used to maintain the device in its safe operating area. power supply 07xsc200 - functional block diagram parallel control inputs mcu interface & output control spi interface self-protected supply mcu interface & output control self-protected high side switches pwm controller high side switches hs0 - hs1 mcu interface
analog integrated circuit device data ? freescale semiconductor 25 07xsc200 4.3.3 mcu interface and output control in normal mode, each bulb is controlled dire ctly from the mcu through the spi. a pulse width modulation control module allows improvement of lamp lifetime with bulb powe r regulation (pwm frequency range from 100 to 400 hz) and addressing the dimming application (day running light). an analog f eedback output provides a cu rrent proportional to the lo ad current or the temperatu re of the board. the spi is used to configur e and to read the diagnostic st atus (faults) of high side outputs. the reported fault conditions are: openload, short-circuit to battery, short-circuit to ground (overcu rrent and severe short-circuit), thermal shutdown, and under/overvoltage. in fail-safe mode, each lamp is controlled with dedicated para llel input pins. the device is configured in default mode.
analog integrated circuit device data ? 26 freescale semiconductor 07xsc200 5 functional device operation 5.1 spi protocol description the spi interface has a full duplex, three- wire synchronous data transfer with four i/o lines associated with it: serial input (si), serial output (so), serial clo ck (sclk), and chip select ( csb ). the si / so pins of the 07xsc200 follow a first-in first-out (d15 to d0) protocol, with both input and output words transferring the most significant bit (msb) first. all inputs are compatible with 5.0 or 3.3 v cmos logic levels. figure 10. single 16-bi t word spi communication 5.2 operational modes the 07xsc200 has four operating modes : sleep, normal, fail-safe and fault. table 5 and figure 12 summarize details contained in succeeding paragraphs. the figure 11 describes an internal signal called in_on[x] depending on in[x] input. figure 11. in_on[x] internal signal the 07xsc200 transits to operating modes according to the following signals: ? wake-up = rstb or wake or in_on[0] or in_on[1] or clock_on, ? fail = (v dd failure and vdd_fail_en) or (watchdog time -out and fsi input not shorted to ground), ? fault = oc[0:1] or ot[0:1] or sc[0:1] or uv or (ov and ov_dis ). cs csb si sclk so d15 d1 d2 d3 d4 d5 d6 d7 d8 d9 d14 d13 d12 d11 d10 od12 d0 od13 od14 od15 od6 od7 od8 od9 od10 od11 od1 od2 od3 od4 od5 1. rstb is in a logic h state during the above operation. 2. do, d1, d2, ... , and d15 relate to the most recent ordered entry of program data into the lux ic notes: od0 csb device. 1. rst b is a logic [1] state during the above operation. 2. d15 : d0 relate to the most recent ordered entry of data into the device. 3. od15 : od0 relate to the first 16 bits of ordered fault and status data out of the device. notes in_on[x] in[x] t in
analog integrated circuit device data ? freescale semiconductor 27 07xsc200 figure 12. operating modes 5.2.1 sleep mode the 07xsc200 is in sleep mode when: ?v pwr and v dd are within the normal voltage range, ? wake-up = 0, ? fail = x, ?fault = x. this is the default mode of the device after first applying battery voltage (v pwr ) prior to any i/o transitions. this is also the state of the device when the wake and rstb , clock_on and in_on[0:1] are logic [0]. in the sleep mode, the output and all unused internal circuitry, such as th e internal regulator, are off to minimize draw current. in addition, all spi-configurable feature s of the device are as if set to logic [0]. in the event of an external v pwr supply disconnect, an unexpected current consum ption may sink on the vdd supply pin (in sleep state). this current leakage is about 70 ma instead of 5.0 a and it may impact the device reliability. the device recovers its normal operational mode once v pwr is reconnected. table 5. 07xsc200 operating modes mode wake-up fail fault comments sleep 0 x x device is in sleep mode. all outputs are off. normal 1 0 0 device is currently in normal mode. watchdog is active if enabled. fail-safe 1 1 0 device is currently in fail-safe mode due to watchdog time-out or v dd failure conditions. the output states are defined with the rfs resistor connected to fsi. fault 1 x 1 device is currently in fault mode. the faulted output(s) is (are) off. the safe auto-retry circuitry is active to turn-on again the output(s). x = don?t care. sleep (fail=0) and (wake-up=1) and (fault=0) (wake-up=0) fail-safe normal (wake-up=0) (fail=1) and (wake-up=1) and (fault=0) (fail=0) and (wake-up=1) and (fault=0) (wake-up=1) and (fail=1) and (fault=0) fault (wake-up=0) (wake-up=1) and (fault=1) (fail=0) and (wake-up=1) and (fault=1) (fail=1) and (wake-up=1) and (fault=1) (fail=0) and (wake-up=1) and (fault=0) (fail=1) and (wake-up=1) and (fault=0)
analog integrated circuit device data ? 28 freescale semiconductor 07xsc200 to avoid this unexpected current leakage on the vdd supply pin, maintain the device in normal mode with rstb pin set to logic[1]. this will allow diagnosis of the battery disconnect ion event through uv fault reporting in spi. then, apply 0 v on the vdd supply pin to switch the device to sleep state. 5.2.2 normal mode the 07xsc200 is in normal mode when: ?v pwr and v dd are within the normal voltage range, ? wake-up = 1, ? fail = 0, ?fault = 0. in this mode, the nm bit is set to lfault_contrologic [1] and the outputs hs[0:1] are under control, as defined by the hson sig nal: hson[x] = (((in[x] and dir_dis [x]) or on bit[x]) and pwm_en ) or (on bit [x] and du ty_cycle[x] and pwm_en). in this mode and also in fail-safe, the fault conditi on reset depends on fault_control signal, as defined below: fault_control[x] = ((in_on[x] and dir_dis [x]) and pwm_en ) or (on bit [x]). 5.2.2.1 programmable pwm module the outputs hs[0:1] are controlled by th e programmable pwm module if pwm_en and on bits are set to logic [1]. the clock frequency from clock input pin or from the internal clock is the factor 2 7 (128) of the output pwm frequency (clock_sel bit). the outputs hs [0:1] can be controlled in the range of 5.0 to 98% with a reso lution of 7 bits of duty cycle ( table 6 ). the state of other in pin is ignored. the timing includes seven programmable pwm switching delay (n umber of pwm clock rising edges) to improve overall emc behavior of the light module ( table 7 ). table 6. output pwm resolution on bit duty cycle output state 0 x off 1 0000000 pwm (1/128 duty cycle) 1 0000001 pwm (2/128 duty cycle) 1 0000010 pwm (3/128 duty cycle) 1 n pwm ((n+1)/128 duty cycle) 1 1111111 fully on table 7. output pwm switching delay delay bits output delay 000 no delay 001 16 pwm clock periods 010 32 pwm clock periods 011 48 pwm clock periods 100 64 pwm clock periods 101 80 pwm clock periods 110 96 pwm clock periods 111 112 pwm clock periods
analog integrated circuit device data ? freescale semiconductor 29 07xsc200 the clock frequency from clock is permanently monitored in orde r to report a clock failure in case the frequency is out a specified frequency range (from f clock(low) to f clock(high) ). in case of clock failure, no pwm feature is provided, the on bit defines the outputs state and the clock_fail bit reports [1]. 5.2.2.2 calibratable internal clock the internal clock can vary as much as ? 30 percent corresponding to typical f pwm(0) output switching period. using the existing spi inputs and the precis ion timing reference already available to the mcu, the 07xsc200 allows clock period setting within ? 10 percent of accuracy. calibrating the internal clock is initiated by defined word to calr register. the calibration pulse is provided by the mcu. the pulse is sent on the csb pin after the spi word is launched. at the moment, the csb pin transitions from logic [1] to [0] until from logic [0] to [1] determines the period of internal clock with a multiplicative fac tor of 128. in case a negative csb pulse is outside a predefined time range (from t csb(min) to t csb(max) ), the calibration event will be ignored and the internal clock will be unaltered or reset to the default value (f pwm(0) ), if this was not calibrated before. the calibratable clock is used, instead of the clock from clock input, when clock_sel is set to [1]. 5.2.3 fail-safe mode the 07xsc200 is in fail-safe mode when: ?v pwr is within the normal voltage range, ? wake-up = 1, ? fail = 1, ?fault = 0. 5.2.3.1 watchdog if the fsi input is not grounded, the watchdog time-out det ection is active when either the wake or in_on[0:1] or rstb input pin transitions from logic [0] to logic [1]. the wake input is capable of bein g pulled up to v pwr with a series of limiting resistance limiting the internal clamp current according to the specification. the watchdog time-out is a multiple of an internal oscillator . as long as the wd bit (d15) of an incoming spi message is toggled within the minimum watchdog time-out period (wdto), the device will operate normally. 5.2.3.2 fail-safe conditions if an internal watchdog time-out occurs before the wd bit for fsi open ( table 8 ) or in case of v dd failure condition (v dd < v dd(fail) )) for vdd_fail_en bit is set to logic [1], the device will revert to a fail-safe mode until the wd bit is written to logic [1] (see fail-safe to normal mode transition paragraph) and v dd is within the normal voltage range. cs si calr si command ignored internal clock duration
analog integrated circuit device data ? 30 freescale semiconductor 07xsc200 during the fail-safe mode, the outputs will depend on the correspon ding input. the spi register content is reset to their defau lt value (except por bit) and fault protections are fully operational. the fail-safe mode can be detected by monitoring the nm bit is set to [0]. 5.2.4 normal & fail-safe mode transitions transition fail-safe to normal mode to leave the fail-safe mode, v dd must be in nominal voltage and the microcontr oller has to send a spi command with wdin bit set to logic [1]; the other bits are not considered. the previous latched faults are reset by the transition into normal mode ( auto- retry included). moreover, the device can be brought out of the fail-safe mode due to watchdog time-out issue by forcing the fsi pin to logic [0 ]. transition normal to fail-safe mode to leave the normal mode, a fail-safe condit ion must occurred (fail=1). the previous la tched faults are reset by the transition into fail-safe mode (auto-retry included). 5.2.5 fault mode the 07xsc200 is in fault mode when: ?v pwr and v dd are within the normal voltage range, ? wake-up = 1, ? fail = x, ?fault=1. this device indicates the faults below as they occur by driving the fs b pin to logic [0] for rstb inpu t is pulled up: ? overtemperature fault, ? overcurrent fault, ? severe short-circuit fault, ? output(s) shorted to v pwr fault in off state, ? openload fault in off state, ? overvoltage fault (enabled by default), ? undervoltage fault. the fs b pin will automatically return to logic [1] when the fault condition is removed, exc ept for overcurrent, se vere short-circuit, overtemperature and undervoltage which will be reset by a new tu rn-on command (each fault_control signal to be toggled). fault information is retained in the spi fault register and is available (and reset) via the so pin during the first valid spi communication. the openload fault in on state is only reported through spi register without effect on the corresponding output state (hs[x]) and the fs pin. 5.2.6 start-up sequence the 07xsc200 enters in normal mode after start-up if following sequence is provided: ? vpwr and vdd power supplies must be above their undervoltage thresholds, ? generate wake-up event (wake-up=1) from 0 to 1 on rstb. the device switches to no rmal mode with spi register content is reset (as defined in table 10 and table 22 ). all features of the 07xsc200 will be available after 50 ? s typical, and all spi registers are set to default values (set to logic [0]). ? toggle wd bit from 0 to 1. and, in case the pwm module is used (pwm_en bit is set to logic [1]) with an external reference clock: table 8. spi watchdog activation typical rfsi ( ? ) watchdog 0 (shorted to ground) disabled (open) enable
analog integrated circuit device data ? freescale semiconductor 31 07xsc200 ? apply pwm clock on clock input pin after maximum 200 ? s (min. 50 ? s). if the correct start-up sequence is not provided, the pwm function is not guaranteed. 5.3 protection and diagnostic features 5.3.1 protections over-temperature fault the 07xsc200 incorporates over-temperature detection and shutdown circuitry for each output structure. two cases need to be considered when th e output temperature is higher than t sd : ? if the output command is on: the correspondi ng output is latched off. fsb will be al so latched to logic [0]. to delatch the fault and be able to turn on again the outputs, the failure cond ition must disappear and the auto -retry circuitry must be activ e, or the corresponding output must be commanded off and then on (toggling fault_control signal of corresponding output) or the v supply(por) condition, if v dd = 0. ? if the output command is off: fsb will go to logic [0 ] till the corresponding output temperature are below t sd . for both cases, the fault register ot[0:1] bit into the status r egister will be set to [1]. the fault bits will be cleared in t he status register after a spi read command. 5.3.1.1 overcurrent fault the 07xsc200 incorporates output shutdown in order to protect each output structure aga inst resistive short- circuit condition. this protection is composed by eight predefined current levels (time dependent) to fit xenon-hid manners by default or, 55 w or 28 w bulb profiles, selectable separately by xenon bit and 28w bits (as illustrated figure 14 , page 39 ). in the first turn-on, the lamp filament is cold and the curr ent will be huge. fault_control sig nal transition from logic [0] to [1] or an auto-retry define this event. in this case, the overcurrent protection will be fitted to inrush current, as shown in figure 5 . this overcurrent protection is programmable: oc [1:0] bits select overcurrent slope speed and ochi1 current step can be removed in case the ochi bit is set to [1]. in steady state, the wire harness will be protected by oclo2 current level by defaul t. three other dc overcurrent levels are available: oclo1 or oclo3 or oclo4 ba sed on the state of the oclo[1,0] bits. if the load current level ever reaches the overcurrent detecti on level, the corresponding outpu t will latch the output off and fsb will be also latched to logic [0]. to delatch the fault and be able to turn on again the corresponding output, the failure cond ition must disappear and the auto-retry circuitr y must be active or the corresponding output must be commanded off and then on (toggling fault_control signal of corresponding output) or v supply(por) condition if v dd = 0. the spi fault report (oc[0:1] bits) is removed after a read operation. in normal mode using internal pwm module, the 07xsc200 inco rporates also a cooling bulb filament management if oc_mode and xenon are set to logic [1]. in this case, the first t step of multi-step overcurrent protec tion will depend to the previous off duration, as illustrated in figure 6 . the following figure illustrates the current le vel will be used in function to the duration of previous off state (toff). the slope of cooling bulb emulator is configurable with ocoffcb[1:0] bits. hson signal over-current thresholds pwm fault_control hson
analog integrated circuit device data ? 32 freescale semiconductor 07xsc200 5.3.1.2 severe short-circuit fault the 07xsc200 provides output shutdown to pr otect each output in case of a severe s hort-circuit during of the output switching. if the short-circuit impedance is below r short, the device will latch the output off, fsb will go to logic [0] and the fault register sc[0:1] bit will be set to [1]. to delatch the fault and be able to turn on again the outputs, the failure condition must disap pear and the corresponding output must be commanded off and then on (toggling fault_control signal of corresponding output) or v supply(por) condition if v dd = 0. the spi fault report (sc[0:1] bits) is removed after a read operation. 5.3.1.3 overvoltage fault (enabled by default) by default, the overvoltage protection is enabled. the 07xsc200 shuts down all outputs and fsb will go to logic [0] during an overvoltage fault condition on the vpwr pin (v pwr > v pwr(ov) ). the outputs remain in the off state until the overvoltage condition is removed (v pwr < v pwr(ov) - v pwr(ovhys) ). when experiencing this fault, the ovf fault bit is set to logic [1] and cleared after either a valid spi read. the overvoltage protection can be disabled through the spi (ov_dis bit is disabled set to logic [1]). the fault register reflec ts any overvoltage condition (v pwr > v pwr(ov) ). this overvoltage diagnosis, as a warning, is removed after a read operation, if the fault condition disappears. the hs[0:1] outputs are not commanded in r ds(on) above the ov threshold. 5.3.1.4 undervoltage fault the output(s) will latch off at some battery voltage below vpwr (uv) . as long as the v dd level stays within the normal specified range, the internal logic stat es within the device will remain (configuration and reporting). in the case where battery voltage dr ops below the undervoltage threshold (v pwr < v pwr(uv) ), the outputs will turn off, fsb will go to logic [0], and the fault register uv bit will be set to [1]. two cases need to be considered when the battery level recovers (v pwr > v pwr(uv)_up ): ? if outputs command are low, fsb will go to logic [1] but the uv bit will remain set to 1 until the next read operation (warnin g report). ? if the output command is on, fsb will remain at logic [0]. to delatch the fault and be able to turn on again the outputs, the failure condition must disappear and the aut o-retry circuitry must be active or the corresponding output must be commanded off and then on (toggling fault_control signal of corresponding output) or v supply(por) condition if v dd = 0. in extended mode , the output is protected by overtemperature shutdown ci rcuitry. all previous latched faults, occurred when v pwr was within the normal voltage range, are guaranteed if v dd is within the operational voltage range or until v supply(por) if vdd = 0. any new ot fault is det ected (vdd failure included) and reported through spi above vpwr (uv) . the output state is not changed as long as the v pwr voltage does not drop any lower than 3.5 v typical. all latched faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if: ?v dd < v dd(fail) with v pwr in nominal voltage range, ?v dd and v pwr supplies is below v supply(por) voltage value. over-current thresholds toff depending to toff cooling pwm hson signal fault_control hson depending on toff
analog integrated circuit device data ? freescale semiconductor 33 07xsc200 figure 13. auto-retry state machine 5.3.2 auto-retry the auto-retry circuitry is used to reactivate the output(s) auto matically in case of overcurrent or overtemperature or undervo ltage failure conditions to provide a high availability of the load. auto-retry feature is available in fault mode. it is activated in ca se of internal retry sign al is set to logic [1]: retry[x] = oc[x] or ot[x] or uv. the feature retries to switch-on the ou tput(s) after one auto-retry period (t auto ) with a limitation in term of number of occurrence (16 for each output). the counter of retry occurrences is reset in case of fail-safe to normal or normal to fail-safe mode transitions. at each auto-retry, the overcu rrent detection will be set to default values in order to sustain the inrush current . the figure 13 describes the auto -retry state machine. 5.3.3 diagnostic output shorted to v pwr fault the 07xsc200 incorporates output shorted to v pwr detection circuitry in off state. output shorted to v pwr fault is detected if output voltage is higher than v osd(thres) and reported as a fault condition when the outp ut is disabled (off ). the output shorted to v pwr fault is latched into the status regist er after the internal gate voltage is pu lled low enough to turn off the output. the os[0:1] and ol_off[0:1] fault bits are set in the status register and fsb pin reports in real time the fault. if the output sho rted to v pwr fault is removed, the status register will be cleared after reading the register. the open output shorted to v pwr protection can be disabled through spi (os_di s[0:1] bit). openload faults the 07xsc200 incorporates three dedicated openload detection circ uitries on the output to detect in off and in on state. off on latched off auto-retry off auto-retry on (sc=1) (ov=1) (fault_control=1 and ov=0) (fault_control=0 or ov=1) (fault_control=0) (fault_control=0) (fault_control=0) (sc=1) (retry=1) => count=count+1 (retry=1) (count=16) (after retry period and ov=0) (openloadoff=1 or shortvpwr=1 (openloadoff=1 or shortvpwr=1 (openloadoff=1 or shortvpwr=1 (openloadon=1) (openloadon=1) or ov=1) or ov=1) or ov=1) if hson=1 if hson=0 if hson=1
analog integrated circuit device data ? 34 freescale semiconductor 07xsc200 5.3.3.1 openload detection in off state the off output openload fault is detected when the out put voltage is higher than v old(thres) pulled up with internal current source ( i old(off) ) and reported as a fault condition when the output is disabled (off). the off output openload fault is latched into the status register or when the internal gate voltage is pulled low eno ugh to turn off the output. the ol_off[0:1] fault b it is set in the status regi ster. if the openload fault is remov ed (fsb output pin goes to high), the status register will be clea red after reading the register. the off output openload protection can be disabled through spi (oloff_dis[0:1] bit). 5.3.3.2 openload detection in on state the on output openload current thresholds can be chosen by the spi to detect a st andard bulbs or leds (olled[0:1] bit set to logic [1]). in the case where load current drops below the de fined current threshold olon bit is set to logic [1], the outpu t stays on and fsb is not disturbed. 5.3.3.3 openload detectio n in on state for led openload for leds only (olled[0:1] set to l ogic [1]) is detected periodically each t olled (fully-on, d[6:0]=7f) . to detect olled in fully-on state, the out put must be on at least t olled. to delatch the diagnosis, the condition should be removed and t he spi read operation is needed (ol_on[0:1] bit). the on output open-load protection can be disabled th rough the spi (olon_dis[0:1] bit). 5.3.3.4 analog current recopy and temperature feedbacks the csns pin is an analog output reporting a current proportiona l to the designed output current or a voltage proportional to t he temperature of the gnd flag (p in #14). the routing is spi programmable (t emp_en, csns_en, csns_s [1,0] and csns_ratio_s bits). in case the current recopy is active, the csns output del ivers current only during on time of the output switch without overshoot. the maximum current is 2.0 ma, typical. the typical value of external csns resistor connected to the ground is 2.5 k ? . the current recopy is not active in fail-safe mode. 5.3.3.5 temperature prewarning detection in normal mode, the 07xsc200 provides a temperature prewarni ng reported via the spi, in case the temperature of the gnd flag is higher than t otwar . this diagnosis (otw bit set to [1]) is latched in the spi diagr0 register . to delatch, a read spi command is needed. 5.3.4 active clamp on vpwr the device provides an active gate clamp circuit in order to limit the maximum transient v pwr voltage at v pwr(clamp) . in case of an overload on an output, the correspondi ng output is turned off, which leads to high voltage at vpwr with an inductive v pwr line. when the v pwr voltage exceeds v pwr(clamp) threshold, the turn-off on the corre sponding output is deactivated and all hs[0:1] outputs are switched on automatically to demagnetize the inductive battery line. 5.3.5 reverse battery on vpwr the output survives t he application of reverse voltage as low as -18 v. under these conditions, the on resistance of the output is two times higher than a typical ohmic value in forward mode . no additional passive components are required except on the v dd current path.
analog integrated circuit device data ? freescale semiconductor 35 07xsc200 5.3.6 ground disconnect protection in the event the 07xsc200 ground is disconnected from load ground, the device protects itself and safely turns off the output, regardless of the state of the output at the time of disconnection (maximum v pwr = 16 v). a 10 k ? resistor needs to be added between the mcu and each digital input pin to ensure the device turns off, during a ground disconnect and to prevent this pin from exceeding maximum ratings. 5.3.7 loss of supply lines 5.3.7.1 loss of v dd if the external v dd supply is disconnected (or not within specification: v dd < v dd (fail) , with the vdd_fail_en bit set to logic [1]), all spi register content is reset. the outputs can still be driven by the direct inputs in[0 : 1] if v pwr is within specified voltage range. the 07xsc200 uses the battery input to power the output mosfet-related current sense ci rcuitry and any other internal logic providing fail-safe devic e operation with no v dd supplied. in this state, the over temperature, overcurrent, severe s hort-circuit, short to vpwr and off openload circuitry are fully operational, with def ault values corresponding to all spi bits are set to logic [0]. no current is conducted from v pwr to v dd . 5.3.7.2 loss of v pwr if the external v pwr supply is disconnected (or not within specification), the spi configuration, report ing, and daisy chain features are provided for rstb to set to logic [1] under v dd in nominal conditions. this fault condition can be diagnosed with uv fault in spi statr_s registers. the spi pull-up and pull-down current so urces are not operational. the pr evious device configuration is maintained. no current is conducted from v dd to v pwr . 5.3.7.3 loss of v pwr and v dd if the external v pwr and v dd supplies are disconnected (or not within specification: (v dd and v pwr ) < v supply(por) ), all spi register contents are reset, with default values corresponding to all spi bits set to logic [0] and all latched faults reset. 5.3.8 emc performances all following tests are performed on the freescale evaluation b oard in accordance with the ty pical application schematic. the device is protected in the event of positive and negative transients on the v pwr line (per iso 7637-2). the 07xsc200 successfully meets the class 5 of the cispr25 emission standard and 200 v/m or bci 200 ma injection level for immunity tests. 5.4 logic commands and registers 5.4.1 serial input communication spi communication is accomplished using 16-bit messages. a messa ge is transmitted by the m cu starting with the msb d15 and ending with the lsb, d0 ( table 9 ). each incoming command message on the si pin can be interpreted using the following bit assignments: the msb, d15, is the watchdog bit (wdin) . in some cases, output selection is done with bit d13. the next four bits, d14 -d12: d10, are used to select the command register. the remaining nine bits, d8 : d0, are used to configure and control the outputs and their protection features. multiple messages can be transm itted in succession to accommodate those applications where daisy-chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. any attempt made to latch in a message that is not 16 bits will be ignored. the 07xsc200 has defined registers, whic h are used to configure the device and to control the state of the outputs. table 10 summarizes the si registers.
analog integrated circuit device data ? 36 freescale semiconductor 07xsc200 ? table 9. si message bit assignment bit sig si msg bit message bit description msb d15 watchdog in: toggled to satisfy watchdog requirements. d13 register address bit used in some cases for output selection ( table 11 ). d14, d12 : d10 register address bits. d9 not used (set to logic [0]). lsb d8:d0 used to configure the inputs, outputs, and the dev ice protection features and so status content. table 10. serial input address and configuration bit map si register si data d15 d1 4 d1 3 d1 2 d1 1 d1 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 statr_ s wdi n x x 0 0 0 0 0 0 0 0 soa4 soa3 soa2 soa1 soa0 pwmr_ s wdi n 1a00 10 28w_s on_s pwm6_s pwm5_s pwm4_s pwm3_s pwm2_s pwm1_s pwm0_s confr 0_s wdi n 1a01 00 0 0 0 dir_dis_ s sr1_s sr0_s delay2_s delay1_ s delay0_ s confr 1_s wdi n 1a0110 0 0 retry_ unlimited_ s retry_dis _s os_dis_s olon_dis _s oloff_di s_s olled_e n_s csns_rati o_s ocr_s wdi n 1 a 1 0 0 0 xenon _s bc1_s bc0_s oc1_s oc0_s ochi_s olco1_s olco0_ s oc_mode _s gcr wdi n 0 0 1010vdd_ fail_ en pwm_en clock_s el temp_en csns_e n csns1 csns0 x ov_dis calr wdi n 0 0 1110 1 0 1 0 1 1 0 1 1 register state after rst =0 or v dd(fail) or v supply (por) condition 000xxx0 0 0 0 0 0 0 0 0 0 x = don?t care. ? s = output selection with the bit a as defined in table 11 .
analog integrated circuit device data ? freescale semiconductor 37 07xsc200 5.4.2 device register addressing the following section describes the possible register add resses (d[14:10]) and their impact on device operation. 5.4.2.1 address xx000 ? status register (statr_s) the statr register is used to read the device status and the va rious configuration register c ontents without disrupting the dev ice operation or the register contents. the regist er bits d[4:0] determine the content of the first sixteen bits of so data. in add ition to the device status, this feature provides the ability to read the content of the pwmr_s, co nfr0_s, confr1_s, ocr_s, gcr and calr registers (refer to serial output communication (d evice status return data) . 5.4.2.2 address a 1 a 0 001? output pwm control re gister (pwmr_s ) the pwmr_s register allows the mcu to control the state of corresponding ou tput through the spi. each output ?s? is independently selected for configuratio n based on the state of the d13 bit ( table 11 ). a logic [1] on bit d8 (28w_s) selects the 28 w overcurrent protection profile: the overcurr ent thresholds are divided by 2, and the inrush and cooling responses are dedicated to 28 w lamps for hs[0,1] outputs. bit d7 sets the output state. a logic [1] enables the corresponding output switch and a logic [0] turns it off (if in input is also pulled down). bits d6:d0 set the output pwm duty cycle to on e of 128 levels for pwm_en is set to logic [1], as shown table 6 . 5.4.2.3 address a 1 a 0 010? output configuration register (confr0_s ) the confr0_s register allows the mcu to configure corresp onding output switching throu gh the spi. each output ?s? is independently selected for configurat ion based on the state of the d14 : d13 bits ( table 11 ). for the selected output, a logic [0] on bit d5 (dir_dis_s) will enable the output for direct control. a logic [1] on bit d5 will disable the output from direct control (in this case, th e output is only controlled by the on bit). d4:d3 bits (sr1_s and sr0_s) are used to select the high or me dium or low speed slew rate for the selected output, the default value [00] corresponds to the medium speed slew rate ( table 12 ). incoming message bits d2 : d0 reflect the desired output that will be delayed of predefined pwm clock rising edges number, as shown table 7 , (only available for pwm_en bit is set to logic [1]). 5.4.2.4 address a 1 a 0 011 ? output configuration register (confr1_s) the confr1_s register allows the mcu to configure corresponding output fault m anagement through the spi. each output ?s? is independently selected for configur ation based on the state of the d14 : d13 bits ( table 11 ). a logic [1] on bit d6 (retry_unlimited_s) disables the auto-r etry counter for the selected output, the default value [0] corresponds to enable auto-retry feature with time limitation. table 11. output selection a (d13) hs selection 0 hs0 (default) 1hs1 table 12. slew rate speed selection sr1_s (d4) sr0_s (d3) slew rate speed 0 0 medium (default) 01low 1 0 high 11not used
analog integrated circuit device data ? 38 freescale semiconductor 07xsc200 a logic [1] on bit d5 (retry_dis_s) disables the auto-retry fo r the selected output, the defaul t value [0] corresponds to enabl e this feature. a logic [1] on bit d4 (os_dis_s) disables the output hard shorted to v pwr protection for the selected output, the default value [0] corresponds to enable this feature. a logic [1] on bit d3 (olon_dis_s) disables the on output openload detection for th e selected output, the default value [0] corresponds to enable this feature ( table 13 ). a logic [1] on bit d2 (oloff_dis_s) disables the off output openload detection for the selected output, the default value [0] corresponds to enable this feature. a logic [1] on bit d1 (olled_en_s) enables the on output openload detection for leds for the selected output, the default value [0] corresponds to on output openload detection is set for bulbs ( table 13 ). a logic [1] on bit d0 (csns_ratio_s) selects the high ratio on the csns pin for the corresponding output. the default value [0] is the low ratio ( table 14 ). 5.4.2.5 address a 1 a 0 100 ? output overcurrent register (ocr) the ocr_s register allows the mcu to configure corresponding output overcurrent protection th rough the spi. each output ?s? is independently selected for configur ation based on the state of the d14 : d13 bits ( table 11 ). a logic [1] on bit d8 ( xenon_s ) disables enables the xenon 55 w or 28 w bulb overcurrent profile, as described figure 14 . table 13. on openload selection olon_dis_s (d3) olled_en_s (d1) on openload detection 0 0 enable with bulb threshold (default) 0 1 enable with led threshold 1 x disable table 14. current sense ratio selection csns_high_s (d0) current sense ratio 0 crs0 (default) 1 crs1
analog integrated circuit device data ? freescale semiconductor 39 07xsc200 figure 14. overcurrent profile depending on x enon bit d[7:6] bits allow to mcu to programmable bulb cooling curve an d d[5:4] bits inrush curve for selected output, as shown table 15 and table 16 . a logic [1] on bit d3 (ochi_s bit) the o chi1 level is replaced by ochi2 during t oc1 , as shown figure 15 . table 15. cooling curve selection bc1_s (d7) bc0_s (d6) profile curves speed 0 0 medium (default) 01 slow 10 fast 1 1 medium table 16. inrush curve selection oc1_s (d5) oc0_s (d4) profile curves speed 0 0 slow (default) 01fast 1 0 medium 1 1 very slow xenon bit set to logic [1]: xenon bit set to logic [0]: i och1 i och2 i oc1 i oc2 i oclo3 i oclo2 i oclo1 i oclo4 t oc1 t oc3 t oc4 t oc5 t oc6 t oc7 time t oc2 t oc1 t oc2 t oc3 t oc4 t oc5 t oc6 t oc7 time i och1 i och2 i oc1 i oc2 i oc3 i oc4 i ocl3 i ocl2 i ocl1 i ocl4
analog integrated circuit device data ? 40 freescale semiconductor 07xsc200 figure 15. overcurrent profile with ochi bit set to ?1? the wire harness is protected by one of four possible current levels in steady state, as defined in table 17 . bit d0 (oc_mode_sel) allows to select the overcurrent mode, as described table 18 . address 00101 ? global configuration register (gcr) the gcr register allows the mcu to configure the device through the spi. bit d8 allows the mcu to enable or disable the v dd failure detector. a logic [1] on vdd_fa il_en bit allows s witch of the outputs hs[0:1] with pwmr register device in fail-safe mode in case of v dd < v dd(fail). bit d7 allows the mcu to enable or disable the pwm module. a logic [1] on pwm_en bit allows control of the outputs hs[0:1] with pwmr register (the direct input states are ignored). bit d6 (clock_sel) allows to select the clock used as reference by pwm module, as described in the following table 19 . bits d5:d4 allow the mcu to select one of two analog feedback on csns output pin, as shown in table 20 . table 17. output steady state selection oclo1 (d2) oclo0 (d1) steady state current 0 0 oclo2 (default) 01 oclo3 10 oclo4 11 oclo1 table 18. overcurrent mode selection oc_mode_s (d0) overcurrent mode 0 only inrush current management (default) 1 inrush current and bulb cooling management table 19. pwm module selection pwm_en (d7) clock_sel (d6) pwm module 0 x pwm module disabled (default) 1 0 pwm module enabled with external clock from clock 1 1 pwm module enabled with internal calibrated clock i och1 i och2 i oc1 i oc2 i oc3 i oc4 i ocl3 i ocl2 i ocl1 t oc1 t oc2 t oc3 t oc4 t oc5 t oc6 t oc7 time i ocl4
analog integrated circuit device data ? freescale semiconductor 41 07xsc200 the gcr register disables the overvoltage pr otection (d0). when this bits is [0], t he overvoltage is enabled (default value). 5.4.2.6 address 00111 ? calibration register (calr) the calr register allows the mcu to calib rate internal clock, as explained in figure 13 . 5.4.3 serial output communicatio n (device status return data) when the csb pin is pulled low, the output register is loaded. meanwhile, the data is cloc ked out msb- (od15-) first as the new message data is clocked into the si pin. the first sixt een bits of data clocking out of the so, and following a csb transition, is dependent upon the previ ously written spi word. any bits clocked out of the serial output (so) pin after the fi rst 16 bits will be representative of the initial message bits c locked into the si pin since the csb pin first transitioned to a logic [0]. this feature is useful for daisy-chaining devices as well as message verification. a valid message length is determined following a csb transition of [0] to [1]. if there is a valid message length, the data is latched into the appropriate registers. a vali d message length is a multiple of 16 bits. at this time, the so pi n is tri-stated and the fault status register is now able to a ccept new fault status information. so data will represent information ranging fr om fault status to register contents, user selected by writing to the statr bits o d4, od3, od2, od1, and od0. the value of the previous bit soa3 will determine which output the so information applies to for the registers which are output spec ific; viz., fault, pwmr, confr0 , confr1, and ocr registers. note that the so data will continue to reflect the information fo r each output that was selected during the most recent statr write until changed with an updated statr write. the output status register correctly refl ects the status of the statr-selected register data at the time that the csb is pulled to a logic [0] during spi communication, and/or fo r the period of time since the last va lid spi communication, with the following exception: ? the previous spi communication was determined to be invalid. in this case, the status will be reported as though the invalid spi communication never occurred ?the v pwr voltage is below 4.0 v, the status must be ignored by the mcu 5.4.4 serial output bit assignment the 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. table 22 , summarizes so returned data for bits od15 : od0. ? bit od15 is the msb; it reflects the state of the watchdog bit from the previously clocked-in message ? bits od14:od10 reflect the state of the bits soa4 : soa0 from the previously clocked in message ? bit od9 is set to logi c [1] in normal mode (nm) ? the contents of bits od8 : od0 depend on bits d4 : d0 from the most recent statr command soa4 : soa0 as explained in the paragraphs following table 22 table 20. csns reporting selection temp_en (d5) csns_en (d4) csns reporting 0 0 csns tri-stated (default) x 1 current recopy of selected output (d3:2] bits) 1 0 temperature on gnd flag table 21. output current recopy selection csns1 (d3) csns0 (d2) csns reporting 10 hs0 11 hs1
analog integrated circuit device data ? 42 freescale semiconductor 07xsc200 5.4.4.1 previous address soa4 : soa0 = 1a000 (statr_s) the returned data od8 reports logic [1] in case of previous power on reset condition (v supply(por) ). this bit is only reset by a read operation. bits od7: od0 reflect the current state of the fault register (fltr) corresponding to the ou tput previously sele cted with the bits soa3 = a ( table 22 ). ? oc_s: overcurrent fault detec tion for a selected output, ? sc_s: severe short-circuit fault detection for a selected output, ? os_s: output shorted to vpwr fa ult detection for a selected output, ? oloff_s: openload in off state fault detection for a selected output, table 22. serial output bit map description previous statr so returned data s o a 4 s o a 3 s o a 2 s o a 1 s o a 0 od 15 od 14 od 13 od 12 od 11 od 10 o d9 od8 od7 od6 od5 od4 od3 od2 od1 od0 statr _s 1 a 0 0 0 wdi n so a4 soa 3 soa 2 so a1 so a0 n m por uv ov olon _s olof f_s os_s ot_s sc_s oc_s pwmr _s 1 a 0 0 1 wdi n so a4 soa 3 soa 2 so a1 so a0 n m 28w _s on_ s pwm 6_s pwm 5_s pwm 4_s pwm3_s pwm2_s pwm1_s pwm0_s conf r0_s 1 a 0 1 0 wdi n so a4 soa 3 soa 2 so a1 so a0 n m x x x dir_d is_s sr1_ s sr0_s delay2_s delay1 _s delay0 _s conf r1_s 1 a 0 1 1 wdi n so a4 soa 3 soa 2 so a1 so a0 n m x x retry_ unlimit ed_s retry_ dis_s os_di s_s olon_dis _s oloff_dis _s olled_ en_s csns_r atio_s ocr_s 1 a 1 0 0 wdi n so a4 soa 3 soa 2 so a1 so a0 n m xeno n_s bc1 _s bc0_ s oc1_ s oc0_ s ochi_s oclo1_s oclo0_ s oc_mod e_s gcr 0 0 1 0 1 wdi n so a4 soa 3 soa 2 so a1 so a0 n m vdd _fai l_e n pw m_e n cloc k_sel temp _en csns _en csns1 csns0 x ov_dis diagr 0 0 0 1 1 1 wdi n so a4 soa 3 soa 2 so a1 so a0 n m x x x x x x clock_fail cal_fail otw diagr 1 0 1 1 1 1 wdi n so a4 soa 3 soa 2 so a1 so a0 n m x x x x in1 in0 x x wd_en diagr 2 1 0 1 1 1 wdi n so a4 soa 3 soa 2 so a1 so a0 n m x x x x x x0 1 0 regist er state after rst = 0 or v dd(f ail) or v supp ly(por ) conditi on n/ a n/ a n/ a n/ a n/ a 0 0 0 0 0 0 0 x 0 0 0 0 00 0 0 s = output selection with the bit a as defined in table 11
analog integrated circuit device data ? freescale semiconductor 43 07xsc200 ? olon_s: openload in on state fault detection (depending on cu rrent level threshold: bulb or led) for a selected output, ? ov: overvoltage fault detection, ? uv: undervoltage fault detection ? por: power on reset detection. the fsb pin reports all faults. for latched faults, this pin is rese t by a new switch off command (toggling fault_control signal). 5.4.4.2 previous address soa4 : soa0 = 1a001 (pwmr_s) the returned data contains the programmed values in the pwmr register for t he output selected with a. 5.4.4.3 previous address soa4 : soa0 = 1a010 (confr0_s) the returned data contains the programmed values in the confr0 register for th e output selected with a. 5.4.4.4 previous address soa4 : soa0 = 1a011 (confr1_s) the returned data contains the programmed values in the confr1 register for th e output selected with a. 5.4.4.5 previous address soa4 : soa0 = 1a100 (ocr_s) the returned data contains the programmed values in the ocr register for th e output selected with a. 5.4.4.6 previous address soa4 : soa0 = 00101 (gcr) the returned data contains the progr ammed values in the gcr register. 5.4.4.7 previous address soa4 : soa0 = 00111 (diagr0) the returned data od2 reports logic [1] in case of pw m clock on clock pin is out of specified frequency range. the returned data od1 reports logic [1 ] in case of calibration failure. the returned data od0 reports logic [1] in case of overte mperature prewarning (temperat ure of gnd flag is above t otwar ). 5.4.4.8 previous address soa4 : soa0 = 01111 (diagr1) the returned data od4: od3 report in real time the state of the direct input in[1:0]. the od0 indicates if the watchdog is enabled (set to logic [1]) or not (set to logic [0]). od4: od1 report the output state in c ase of fail-safe state due to watchdog ti me-out as explained in the following table 23 . 5.4.4.9 previous address soa4 : soa0 = 10111 (diagr2) the returned data is the product id. bits od 2:od0 are set to 010 for protected dual 7.0 m ? high side switches. table 23. watchdog activation report wd_en (od0) spi watchdog 0 disabled 1 enabled
analog integrated circuit device data ? 44 freescale semiconductor 07xsc200 5.4.4.10 default device configuration the default device configuration is explained by the following: ? hs output is commanded by the corresponding in input or on bit through the spi. the medium slew-rate is used, ? hs output is fully protected by the xenon overcurrent profile by default, the severe short-ci rcuit protection, the undervoltag e and the overtemperature protection. the auto-retry feature is enabled, ? openload in on and off state and hs shorted to v pwr detections are available, ? no current recopy and no anal og temperature feedback active, ? overvoltage protection is enabled, ? so reporting fault status must be ignored, ?v dd failure detection is disabled.
analog integrated circuit device data ? freescale semiconductor 45 07xsc200 6 typical applications the following figure shows a typical lighting application (only one vehicle corner) using an external pwm clock from the main mcu. a redundancy circuitry has been implemented to substitute light control (from mcu to watchdog) in case of a fail-safe condition. it is recommended to locate a 22 nf decoupling capacitor to the module connector. spdl07 soic i/o v dd v dd v pwr gnd mcu voltage regulator v pwr hs0 hs1 vdd wake fsb clock in1 sclk csb si so fsi rstb in0 100 nf i/o i/o sclk csb si so 10 k 10 k 10 k 10 k 10 k 10 k 2.5 k 10 k load 0 load 1 csns a/d v dd v dd v pwr v dd 22 nf 22 nf 22 nf 10 k watchdog direct light commands (pedal, comodo,...) vpwr ignition switch 100 nf 10 f 100 nf 10 f 100 nf 100 nf vpwr
analog integrated circuit device data ? 46 freescale semiconductor 07xsc200 7 packaging 7.1 soldering information the 07xsc200 is packaged in a surface mount power package in tended to be soldered directly on the printed circuit board. the 07xsc200 was qualified in accordance with jedec standard s j-std-020c pb-free reflow profile. the maximum peak temperature during the soldering process should not exceed 260 c for 40 seconds maximum duration.
analog integrated circuit device data ? freescale semiconductor 47 07xsc200 7.2 package dimensions package dimensions are provided in package drawings. to find the most current package outline drawing, go to www.freescale.com and perform a keyword sear ch for the drawing?s document number. package suffix package outline drawing number 32-pin soicw ek 98asa00368d ek suffix 32-pin soicw 98asa00368d rev. 0
analog integrated circuit device data ? 48 freescale semiconductor 07xsc200 ek suffix 32-pin soicw 98asa00368d rev. 0
analog integrated circuit device data ? freescale semiconductor 49 07xsc200 ek suffix 32-pin soicw 98asa00368d rev. 0
analog integrated circuit device data ? 50 freescale semiconductor 07xsc200 8 revision history revision date description of changes 1.0 8/2013 ? initial release based on mc07xs3200 data sheet. 2.0 9/2013 ? added the note ?to achieve high reliability over 10 years of continuous operation, the device's continuous operating junction te mperature should not exceed 125 ? ? c.? to operating temperature
document number: mc07xsc200 rev. 2.0 9/2013 information in this document is provided solely to enable sys tem and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without fu rther notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or s pecifications can and do vary in diff erent applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditi ons of sale, which can be found at the following address: freescale.com/salestermsandconditions . freescale and the freescale logo, are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. smartmos is a trademark of freescale semiconductor, inc. a ll other product or service names are the property of their respective owners. ? 2013 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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